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C5 Design Rules and Process Information

  • Design information for the C5 0.5u process is available here.
  • Use the MOSIS Scalable CMOS (SCMOS) SUBM design rules for your ece510 layouts. The design rules can be found in this document. Note that the design rules are given in terms of lambda (=0.3u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.3u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.3u=3.6u in Virtuoso layout.
  • Process information including sheet resistances and transistor parameters can be found here. Click on any of the process runs for required information.
  • Corner models for the C5 process are already available on the AMS server. They are usually located on the MOSIS site here.
on_semi_c5_process_information.txt · Last modified: 2016/09/17 15:16 (external edit)