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cadence_setup_for_ece_614_-_advanced_analog_ic_design_course

Cadence setup for ECE 614 - Advanced Analog IC Design

We will be using IBM 130n CMOS (8RF-DM) process for homeworks and projects in this course. Following steps are requires to get going with the PDK.

  • Sign the MOSIS NDA (Non-disclosure Agreement) with the instructor.

You can not post any proprietary information related to the PDK or the CMOS process online, or discuss on any public message board or forum.

Setting up the course directory

  • Copy the course setup directory ece614_work from /home/pdks/IBM_PDK/ restrict the permissions
cp  –r  /home/pdks/IBM_PDK/ece614_work/   ./
chmod  700  ece614_work
  • You may want to copy the .bashrc file from the copied directory to you home directory
cd ece614_work
cp .bashrc ../

Using Cadence

  • Open a terminal window, and then go to the ece614_work directory and use “virtuoso &” command to start Cadence.
cd ece614_work
virtuoso &
  • In the Library Manager, the models can be viewed in the library cmrf8sf
  • The bindkeys are set to be similar to the NCSU PDK bindkeys used in earlier courses. However, some variations may occur which you can figure out using the command menu.

Creating New Library

Always create new libraries using IBM_PDK command view.

  • Create new library using the steps in the CIW window:
    • IBM_PDK → Library → Create
    • After entering the library name, select Add to existing technology library and choose cmrf8sf.
    • Select Number of levels of metal to 3-2 (this defines the metal stack used in the process i.e. 3 routing and 2 top metal layers.)
  • Start designing with an inverter and see if you can simulate the design.
  • Some examples will be inserted and referred in your cds.lib as the course progresses.

Spectre models location

The Spectre models for the 1BM 130n CMOS process are located at:

/home/pdks/IBM_PDK/cmrf8sf/relDM/Spectre/models

  • For Spectre simulations select the models allModels.scs and design.scs.
  • Choose the appropriate model card for allModels.scs e.g. tt (typical-typical corner) or sf, fs, ff, ssf (slowest corner).

Not selecting a model corner will lead to simulation failure.

PDK Documentation

  • PDK and process documentation can be found at:
/home/pdks/IBM_PDK/cmrf8sf/relDM/doc

Refer to the files Model Guide and Design Manual.

  • Application notes and process training slides can be found at:
/home/pdks/IBM_PDK/cmrf8sf/App Notes

Going through the PDK training and device models datasheet is advised before/during your design work.

CMOS book examples will not work with the ece614 130n CMOS setup, due to PDK incompatibility. You can run the book examples with the ece510 setup.

Change Bindkeys to Default

If you are used to the default bindkeys from the NCSU design kit, comment the following line in the .cdsinit file in your cadence work directory.

 
;; Do not use IBM Bindkeys
;;load(strcat( ibmPdkPath "cmrf8sf/V1.7.0.2DM/cdslib/Skill/ibmPdkBindkeys.il"))
cadence_setup_for_ece_614_-_advanced_analog_ic_design_course.txt · Last modified: 2016/09/17 15:16 (external edit)