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cadence_setup_for_ece_5_418_-_memory_clock_synchronization_ic_design_course

Cadence Setup for ECE 5/418 - PLL IC Design Course

* For the course project and some HW problems, we will use TSMC 180n CMOS process. Since the PDK can't be made freely available, we will use NCSU library symbols in conjunction with the TSMC models.

Spectre Models location on the AMS servers

HW problems and the course project specifically require 180n CMOS models. These models are located at:

/home/pdks/Cadence_IC61_CMOSedu/models/tsmc018.scs

For TSMC 180n CMOS: Select the models tsmc018.scs in the ADE window models setup. Make sure that the model name in your schematic symbol is same as in the model card.

180n Simulation Setup Slides

See 180n CMOS simulation setup information slides.

cadence_setup_for_ece_5_418_-_memory_clock_synchronization_ic_design_course.txt · Last modified: 2016/09/17 15:16 (external edit)